1. Field of the Invention
The present invention relates to a circuit for generating a switching control signal for controlling a switch to connect a data from a bit line to a main amplifier, and in particular to an improved circuit for generating a switching control signal which is capable of reducing a bit line noise in the read mode and an error bit line data in the write mode.
2. Description of the Background Art
Recently, the DRAM uses an internally-downed voltage for a memory cell and a predetermined element. For example, if an external voltage VCC is 3.3V, the internal voltage VDL for an array and memory cell is 2.5V.
As shown in FIG. 1, the known read/write control circuit includes Y-decoders YDEC for decoding Y-addresses YADD inputted, drivers YSD for receiving the output signals from the Y-decoders YDEC, being driven by an internal voltage VDL and outputting a switching control signal YS, a sense amplifier SA for being controlled by a sense amplifier enabling signal SAEN and an inverted signal SAEN, amplifying a data of a bit line, writing the amplified data into a memory cell, reading a data from the memory cell, amplifying the read data and outputting the amplified data to an input/output line, switches YSSW for being turned ON/OFF by the switching control signal YS and outputting the data amplified by the sense amplifier SA to an input/output line or the data of the input/output line to the sense amplifier, and a main amplifier for receiving a main sense amplifier enabling signal, a write enabling bar signal and a read enabling bar signal, respectively, and amplifying and outputting the data of the input/output line.
Here, the switches YSSW are connected in series with the bit line, respectively and each include NMOS transistors NM1 and NM2 receiving the YS signal YS, to each of which a gate is commonly connected, respectively.
The operation of the known read/write control circuit will now be explained with reference to the accompanying drawings.
In the read mode, when the word line is enabled and the data is outputted from the memory cell to the bit line, the sense amplifier SA is enabled by the sense amplifier enabling signal SAEN for thus amplifying the bit line data.
The Y-address signal YADD is decoded by the Y-decoder YDEC, and the switching control signal YS is outputted by the driver YSD. Here, the driver YSD is controlled by the internal voltage VDL which decreases the external voltage VCC inside the chip.
Therefore, the amplified bit line data is switched by the switch YSSW which is controlled by the switching control signal YS and is outputted to the main amplifier MA through the input/output line. The main amplifier MA is enabled by the main amplifier enabling signal MAEN and the read enabling bar signal RENB and amplifies the input/output line data and outputs to the outside of the chip.
On the contrary, in the write mode, the data is inputted into the main amplifier MA from the outside of the chip, and then the main amplifier MA is enabled by the main amplifier enabling signal MAEN and the write enabling bar signal WENB and amplifies the data and outputs to the input/output line.
The data is outputted to the bit line through the switches YSSW and is amplified by the sense amplifier SA and is written into the memory cell.
In the known driver YSD, the switching control signal YS is driven by the identical internal voltage VDL even though the input/output line and bit line are differently operated in the read and write modes.
In this case, as shown in FIG. 2A, since the resistance value is high when the switches YSSW are operated, no problems occur in the read mode due to a small bit line noise. However, when writing a data into the memory cell, since the switching control signal YS is a pulse signal, a shown in FIG. 2B, the switch YSSW is closed in a state that the data are not fully amplified. At this time, if the switch YSSW is directly opened in the read mode, the bit line data may be lost.
When driving the driver using an external voltage VCC, the resistance value of the switch YSSW is decreased, and a quick amplifying operation is implemented. Therefore, it is possible to prevent the error which occurs in the write mode as shown in FIG. 3B. However, in the read mode, as shown in FIG. 3A, the bit line noise is increased due to a current flow between the input/output line and the bit line.